From the 45 nm process for a CMOS integrated circuit, as the feature size of the device is continuously shrinking, an equivalent oxide thickness (EOT) of a gate insulating dielectric layer needs to be reduced synchronously so as to suppress a short channel effect. However, an ultrathin conventional oxide layer or oxide nitride layer will leads to a serious gate leakage. Therefore, the conventional structure of a polycrystalline silicon/SiON gate stack cannot be applied to a device with a small size.
One solution employs a conventional planar CMOS dual-metal gate integrating process and its typical manufacturing method is as follows: dummy gate stack structures are formed in a PMOS region and a NMOS region, respectively; gate spacers are formed on a substrate on both sides of the dummy gate stack structures and a source/drain region are formed on the substrate; an interlayer dielectric layer (ILD) is spin coated on the whole device; the dummy gate stack, structures are selectively removed; and gate trenches are formed in the PMOS region and the NMOS region, respectively; a liner layer (IL) of silicon oxide and a gate insulating layer with a high dielectric constant (HK) are deposited in all the gate trenches; a first barrier layer (BR1) of TiN, an etching stop layer of TaN and a PMOS work function metal layer of TiN are formed by deposition in turn on the gate insulating layer in all of the gate trenches; the PMOS work function metal layer of TiN in the NMOS region is selectively removed by etching until being stopped at the etching stop layer of TaN or the first barrier layer of TiN; an NMOS work function metal layer of TiAl, a third barrier layer of TiN or Al, and a filling layer of Al or W are deposited in turn on the whole device; the CMP planarization is performed until the ILD is exposed; and then a source/drain contact holes are etched to accomplish an electrical connection of the device. During this process, since the work function layer of the NMOS region is TiAl in which the Al ions facilitate a rapid diffusion and may effectively diffuses to proximity of an interface of HK/BR1, it may effectively control the work function of the NMOS region. However, such a process in which a plurality of stack layers are deposited and then selectively removed leads to an excessive number of thin films stacked in the PMOS region and leads to an over-complex gate structure. In case of the length of gate is reduced, a space for the filling layer with a lower resistance is decreased and may lead to issues such as an uneven filling, formation of cavity, or the like. In addition, when devices with different thresholds are formed by adjusting the plurality of NMOS and PMOS regions; a conventional technical solution is to adjust the thickness of the first barrier layer BR1 of TiN or that of the etching stop layer of Ta or TaN, or the thickness and material characteristics of the work function layer, or to select an appropriate annealing temperature of the metal gate. However, the adjusting accuracy of the thickness by these adjusting processes cannot be effectively improved due to the continuous shrinking of the device size, and the process cost caused by material are higher and makes against mass production of the devices.
Another technical solution for suppressing the short channel effect is to employ a FinFET (Fin Field Effect Transistor) and the steps of its typical manufacturing method are shown as follows: a substrate is etched to form a plurality of fins and trenches between the fins extending along a first direction; an insulating dielectric is filled and etched back in the trenches between the fins so as to form a shallow trench isolation (STI); a dummy gate stack structure extending along a second direction is formed on the FIN structure exposing the STI; gate spacers and a source/drain region are formed on both sides of the dummy gate stack structure along the first direction; an interlayer dielectric layer (ILD) is deposited to cover the whole device; the dummy gate stack is selectively removed to leave a gate trench in the ILD layer; and a gate stack structure of HK/MG is deposited in turn in the gate trench. Such a device structure effectively implements a device with a small size and maintains the electrical characteristic of the original design by a 3D channel. However, the integration process of the metal gate for the FinFET continues employing a planar structure and planar integrating method, and the formation of a 3D channel results in the linewidth of the gate length of the gate trench and the HK/MG gate stack formed by filling the gate trench continues to be decreased and its depth-width ratio continues to be increased. Therefore, the issue of filling metal becomes increasingly important for the next generation of device integration. It is in a great need of a new method or new structure to improve the filling ratio of the metal gate for the device with a small size. In addition, since the doping concentration of the channel region formed below the gate stack by utilizing a Fin structure in the FinFET is lower, a conventional manner of adjusting the threshold voltage by the doping of channel is not applicable any longer. There is a difficulty in accurately adjusting and controlling the threshold voltage of the FinFET. Furthermore, in a developing trend of the thickness of the metal gate and the simplifying of the structure, it is increasingly difficult to adjust the work function or threshold values by simply changing thickness of the work function layer or the barrier layer.